d-Matrix Corsair: Digital In-Memory
Compute for AI Inference

The Memory Wall Problem

Modern large-language-model inference is dominated by the decode phase — the autoregressive, token-by-token generation that produces output text. Unlike prefill (which is compute-bound and parallelisable), decode is fundamentally memory-bandwidth-bound: each new token requires reading the full model weights and KV-cache from memory.

GPUs were designed for massively parallel floating-point arithmetic, not for the memory-fetch-dominated workload that decode represents. The result is a “memory wall” — GPU cores sit idle waiting for data to arrive from HBM, and energy is wasted shuttling billions of parameters back and forth across the memory bus every generation step.

Digital In-Memory Compute

d-Matrix Corsair takes a fundamentally different approach: move the computation to where the data already lives. Corsair's Nighthawk chip embeds compute logic directly alongside SRAM cells, allowing matrix-multiply and accumulate operations to execute in-place — without moving weights across a memory bus.

Unlike analogue in-memory compute approaches, Corsair is fully digital. Every operation is deterministic and bit-exact, avoiding the noise and precision issues that have stalled analogue alternatives. The chip ships in a standard PCIe form factor — slot it into any server rack alongside existing GPUs for a heterogeneous prefill + decode pipeline.

Production & Recognition

d-Matrix announced full production of Corsair in June 2026 — the first DIMC accelerator to ship at volume, with design wins at multiple hyperscalers. Corsair received the AI Processor Innovation Award at the 2026 Linley Fall Processor Conference, and d-Matrix has raised over $160 million to scale manufacturing.

Performance: Heterogeneous Inference

Independent benchmarking by Gimlet Labs demonstrated that pairing Corsair with GPUs in a heterogeneous pipeline — GPU for prefill, Corsair for decode — delivers dramatic improvements over GPU-only setups:

The Agentic AI Opportunity

The shift to agentic AI — autonomous coding assistants like Claude Code, multi-tool orchestration frameworks like OpenClaw, and always-on enterprise copilots — has fundamentally changed inference demand patterns. Agentic workloads are decode-heavy and latency-sensitive: an agent making 50+ sequential tool calls cannot tolerate multi-second generation latency at each step.

For these workloads, raw training FLOPS are irrelevant. What matters is time-to-first-token and tokens-per-second during decode. This is precisely the domain where Corsair's architecture excels — turning what was a 24-second wait into a sub-2-second response, making true real-time agentic pipelines viable at scale.

AGICY Phase 3: Decode-Optimised Inference

AGICY's sovereign AI infrastructure roadmap is built around workload-specific silicon — deploying the right accelerator for each computational stage:

• Phase 1 — Tenstorrent RISC-V: Open-ISA Galaxy servers for sovereign LLM inference. Currently in deployment.
• Phase 2 — Cerebras Wafer-Scale: WSE-3 engines for on-premises training and fine-tuning.
• Phase 3 — d-Matrix Corsair: DIMC decode offload via PCIe, pairing with Tenstorrent prefill for a heterogeneous pipeline.

Each phase addresses a distinct bottleneck — inference cost, training sovereignty, and decode latency — with purpose-built hardware, ensuring no single-vendor lock-in. Corsair remains evaluation / roadmap optionality (pre-COD) — not Phase 1 CapEx SSOT. See the d-Matrix Corsair hardware sheet.